Starting at address zero and incrementing by one for each line, four for each instruction.
/E HEX
LTCH INC /LD /INC /DEC LTCH /WR LTCH /RST LTCH /RD INS /E ROM
INS PC ACC ACC ACC REG REG FLAG JMPL JMPE JMPG PC OUT REG DATA IN 0 1
FETCH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7F FF
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
LIT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 FF FD
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 DF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 FF FD
LOAD 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 FF FB
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 DF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 FF FB
STORE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 FD FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
INC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 EF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
DEC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 F7 FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
REG 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 FB FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
CMPL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 FF FD
1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 FE FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 FF FD
CMPR 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 FF FB
1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 FE FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 FF FB
RST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 FF EF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
JUMPL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 FF 7F
1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 FF EF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
JUMPE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 FF BF
1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 FF EF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
JUMPG 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 FF DF
1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 FF EF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
IN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FF FE
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 DF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FF FE
OUT 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 FF FB
1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 FF F7
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 FF FB
NOP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FF FF
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(c) Jon Qualey, December 2006
Back to 4 bit CPU Micro-instruction logic.